NOTE: FESA and ABIS have been superseded by the NEXIS and XENA
chips.
An
integrated circuit for the fast readout of solid-state x-ray and gamma
ray detectors with multi-energy capability, designed for the high-throughput
Automated Baggage Inspection System (ABIS*) and similar x-ray imaging
technologies
Applications
The FESA™ chip is a 32-channel signal processor IC intended for
use with solid-state radiation detectors. It is designed for detecting
x-ray photons at high count rates, up to three million events per second
per channel, with an energy resolution of a few keV. Typical applications
of the FESA™ chip include baggage or package inspection and bone
densitometry. These procedures require x-ray detection at high photon
flux at two to three or at most five energy levels, in order to image
the average atomic number of the irradiated sample with high spatial resolution.
The FESA™ has been successfully implemented in the prototype detector
arms built for the ABIS project*. It allows for discrimination of the
spectral signatures of scanned objects, thus making it a key enabling
technology for automated material recognition.
Availability
The FESA™ chip in its current version is mounted on a custom ceramic
carrier and has mostly been dedicated for use in ABIS*. A demonstration
of its capabilities is available by request: this would showcase ABIS-style
detector module boards equipped with CZT detector arrays and the data
acquisition software. The FESA™ is currently being redesigned for
enhanced features (more channels, wider energy range) and fabrication
using a submicron process. It is expected to be available in 2002. Custom
versions of this chip for specific Nondestructive Evaluation or Inspection
applications are also being considered; inquiries into these possibilities
are welcome.
*ABIS is a real-time computer tomography inspection system
developed under the sponsorship of the Army ARDEC and USDA/APHIS as a
collaborative effort involving NOVA, ENSCO, eV PRODUCTS and X-Ray &
Specialty Instruments.
Specifications
Number of Channels: |
32 + two test channels |
Data Readout: |
160 counters read out sequentially over an 18-bit
parallel data bus |
Readout Time: |
1/4 20 µ for all 160 counters |
Counter dynamic range: |
> 106 counts per second per channel |
Count rate capability: |
> 106 counts per second per channel |
Energy counting bins per channel: |
5 |
Comparator for Levels: |
Independent comparator threshold voltages, 1/4
1.5-3.5V range common to all channels |
Comparator hysteresis: |
25 mV for threshold levels 0 and 1, 50 mV for
levels 2, 3, and 4. |
Threshold offset channel-channel: |
Adjustable baseline using 8-bit DAC with 1/4 16mV
step size |
Input loading capacitance: |
2 pF optimum |
Pulse shaping time: |
Externally adjustable in two ranges: 60 - 300
ns and 350 - 1.5 µ |
Input energy range: |
30-300 keV |
Input referred noise: |
approximately = 1000 e rms (1/4 4.5 keV for CZT) |
Multiple Chip Readout: |
In series up to 16 daisy-chained,
sharing same data bus; or, in parallel using separate data paths |
Die size: |
7.3 x 10.0 mm2 |
Input pad spacing: |
0.25 mm on die |
Images
 A
prototype ABIS detector arm
 Radiographic
image of suitcase
Documents
- ABIS™ Brochure with Specifications
- FESA™ Brochure with Specifications
- IEEE paper "Front-End
Electronics for Spectroscopy Applications (FESA) IC"
- SPIE paper "Scanned
X-Ray Images from a Linear CdZnTe Pad Array with Monolithic Readout
Electronics"
- Paper presented at
the Conference on Applications of Nuclear Techiques "CdZnTe Detectors
for High-Flux X-Ray Imaging"
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